//******************************************************************/
//版本说明:
//V0.1		2013-10-21	11:00	yshao	锐拓5971灯条定制程序
//V0.2		2013-11-06	15:23	yshao	灯条标准程序
//******************************************************************/
`timescale	1ps/1ps
module SL909_N01(
		input	wire		sys_resetb,
                input	wire		sclkin,
                inout   tri             key_in,
                
                output  wire            cpanel_g,
                output  wire            cpanel_r,
                input   wire            cpanel_key,
                
                output	wire		port_da,
                output	wire		port_db,
                inout	wire		sda,
                output	wire		scl,		
                

		//input	wire		flash_SO,      
		//output	wire		flash_SCK,     
		//output	wire		flash_SI,
		//output	wire		flash_CS_n,      

		output	wire		sa_clk,
		output	wire	[2:0]	sa_cnt,
		output	wire		sa_dqm_l,
		output	wire		sa_dqm_h,
		output	wire	[10:0]	sa_addr,
                output	wire	[1:0]	sa_bank,
		inout	tri	[31:0]	sa_data,

		input	wire		mcu_mode,
		input	wire		mcu_spi_cs,
		input	wire		mcu_spi_clk,
		input	wire		mcu_spi_mosi,
		output	wire		mcu_spi_miso,

		input	wire		spi2_cs,
		input	wire		spi2_mosi,
		output	wire		spi2_miso,
		input	wire		spi2_clk,
								
		output	wire		reset_phy,
		
		input	wire		gp0_rxc,
		input	wire		gp0_rxdv,
		input	wire	[3:0]	gp0_rxd,
		output	wire		gp0_txc,
		output	wire		gp0_txen,
		output	wire	[3:0]	gp0_txd,
		
		input	wire		gp1_rxc,
		input	wire		gp1_rxdv,
		input	wire	[3:0]	gp1_rxd,
		output	wire		gp1_txc,
		output	wire		gp1_txen,
		output	wire	[3:0]	gp1_txd,

//		output	wire	[31:0]	porta_data,
		inout	tri	[3:0]	porta_h_sel,
		output	wire		porta_clk,
		output	wire		porta_load,
		output	wire		porta_oe,
		inout	tri	[31:0]	portb_data,
		inout	tri	[3:0]	portb_h_sel,
		output	wire		portb_clk,
		output	wire		portb_load,
		output	wire		portb_oe,
		
		//output	wire		fi_oe,
		//output	wire		fo_oe,
		
		output	wire		mdc,
		inout	tri		mdio,
		
		input   wire            bd_clk,
		output   wire            bd_din,
		input   wire            bd_en,
		output  wire            bd_dout,
		
                output  wire            io_dir,
		inout	tri		led_g,
		output	wire		led_r,
		input   wire            in_nc_A
		);

//******************************************************************/
//			   参数定义
//******************************************************************/
parameter	Sim_Mode	=0;

//****************************************************************
//		内部信号
//****************************************************************
wire		oclk,tclk;
wire            resetb,lock_out;
wire		pll_reset;
wire		time_1ms,time_125ms,time_250ms;
wire		time_1ms_sync,time_16us_sync,time_15ms_sync,time_250ms_sync,time_1s_sync;

wire		gp0_rx_clk,gp1_rx_clk,sclk_in,sclk;

wire	[10:0]	obuf_raddr;
wire	[71:0]	obuf_rdata;
wire		out_clk;
wire		o_sync_flag,o_sclk,o_load,o_loeb;
wire	[4:0]	o_h_sel;
wire	[71:0]	o_data;
wire	[3:0]	adjust_bit;

wire		gp0_rx_dv,gp0_tx_en,gp1_rx_dv,gp1_tx_en;
wire	[7:0]	gp0_rx_data,gp0_tx_data,gp1_rx_data,gp1_tx_data;
wire		gp0_rec_flag,gp0_rec_error,gp1_rec_flag,gp1_rec_error,gp0_rec_error_t,gp1_rec_error_t;
wire		gp0_blank_flag,gp1_blank_flag,redu_flag,blank_flag;
wire		gp0_send_flag,gp0_pre_flag,gp1_send_flag,gp1_pre_flag;
wire	[7:0]	gp0_rec_data,gp1_rec_data,gp0_send_data,gp1_send_data;
wire		rec_flag,rec_error,send_flag,pre_flag;
wire	[7:0]	rec_data,send_data;
wire	[1:0]	rec_vendor;

wire		op_start_flag,fpga_rec_flag,fpga_rec_end,fpga_send_flag,fpga_send_end,send_buf_we;
wire	[7:0]	op_length;
wire	[31:0]	op_start_addr;
wire	[7:0]	rec_buf_raddr,rec_buf_rdata,send_buf_waddr,send_buf_wdata;

wire		vs,hs;
wire	[7:0]	data;
wire	[10:0]	h_num;
wire    [10:0]  h_total_reg,l_total_reg,h_total,l_total;
wire		vs_a,hs_a;
wire	[7:0]	data_a;
wire	[10:0]	h_num_a,h_num_b;
wire	[15:0]	data_b;
wire	[5:0]	cycle_max;
wire            correct_pixel128,correct_enable;
wire	[10:0]	info_addr;
wire	[7:0]	info_data;
wire	[1:0]	unit_color_addr;
wire	[15:0]	unit_color_adj;
wire		unit_color_valid;
wire		adj_h_start,adj_rd_start2,adj_read_end;
wire	[8:0]	adj_h_num;
wire	[9:0]	adjust_addr;
wire	[47:0]	adjust_data;

wire		v_start;
wire		hs_b;

wire		init_mode,init_end,reboot_en_fpga,reboot_en,comm_en;
wire		flash_rec_end,flash_send_end,display_rec_end,display_send_end;
wire		flash_buf_we,display_buf_we;
wire	[7:0]	flash_buf_raddr,flash_buf_waddr,flash_buf_wdata;
wire	[7:0]	display_buf_raddr,display_buf_waddr,display_buf_wdata;
wire		read_start,read_end,read_d_ok,set_d_ok;
wire	[15:0]	set_addr;
wire	[23:0]	start_addr;
wire	[7:0]	read_data,set_data,state_addr;
wire	[7:0]	state_data,bd_state_data,state,state_2,fpga_state_data,dmx_state_data;

wire		black_mark;
wire    [7:0]   unit_pixel_w_max;

wire    [1:0]   pixel_mode;
wire	[4:0]	scan_num;
wire    [3:0]   bit_num;
wire	[7:0]	unit_num;
wire    [1:0]   color_count;
wire		obuf_sel,obuf_sync;
wire    [7:0]   unit_l_max;
wire            data_inv_en;
wire    [7:0]   unit_type;
wire    [4:0]	scan_h_max;
wire    [7:0]   signal_ctrl;
wire    [7:0]   shift_length_per_unit;

wire		flash_ms,input_active;
wire	[7:0]	no_vs_set;
reg		black_flag;

wire		shift_sync,display_sync,force_sync,more_adj_flag;
wire	[12:0]	shift_cycle_adj;

wire	[23:0]	sync_tout,o_tout;
wire		r_frame_sync;

//added by yluo@2010-12-1
wire		init_correct_d_ok;
wire	[18:0]	init_correct_addr;
wire	[7:0]   init_correct_data;
wire            load_picture_flag,load_adj_flag;
reg	[10:0]	key_reboot_count;
wire	[23:0]	tout,sd_tout;

wire            local_test_en,local_picture_en;
wire		press_detect;
wire            key_input;
wire            black;

wire            port_20_en,port_24_en,mode_port_free,empty_down,empty_right;
wire		flash_SO;      
wire		flash_SCK;     
wire		flash_SI;
wire		flash_CS_n;
wire            w_flag;
reg	[2:0]	reset_dcm_cnt;
reg		reset_dcm_flag;
reg		reset_dcm_150;
wire		clk_ok_n;
reg		clk_ok_n_t;
wire		tx_err_en;
wire            r_flag;
reg		init_end_flag=0;
wire            rec_error_sync;
wire    [8:0]   cascade_light;
wire    [7:0]   SR_set;
wire            o_hoeb;
wire            SR1,SR2; 

reg             set_state_ini,read_eeprom;
wire    [31:0]  read_eep_addr;
wire            read_eep_en;
wire            eep_d_ok;
wire    [7:0]   eep_data;    

wire	[7:0]	bd_wdata;
wire		bd_wen;
wire	[4:0]	bd_waddr;                  
wire    [4:0]   bd_raddr;
wire    [7:0]   bd_rdata;   

wire    [7:0]   table_unit_num,RVport_mode;
wire    [15:0]  unit_table_dout;
wire            cc_96_16;
wire            cc_128_16;
wire            cc_256_16;
wire            lc_256_8;    
wire    [8:0]   l_total_reg_b;
wire            h_b_end,h_b_start;
wire    [15:0]  g_tout;            
wire            RV_2,RV2_26pin;
wire    [79:0]  out;
wire	[7:0]	disp_tout,m_tout,correct_type;
wire	[31:0]	out_tout;
reg            testmode_ini_err;
wire            inner_led_g,press;

wire		t_us, t_ms, t_s;
wire	[1:0]	gp0_rx_type,gp1_rx_type;
wire		gp0_tx_clk,gp1_tx_clk,clk_25M;
wire		yt_vs_pre;

//DMX ACK
wire	[7:0]	dmx_ack_in;

wire		mem_err_sel;	//0:mem处理流程。1:err处理流程。
wire	[3:0]	clk_sel;	//接收DMX数据对应时钟，0:2M时钟，1：0.25M时钟,其余：保留
wire	[2:0]	err_port_num;
wire		err_read_start;
wire	[3:0]	mem_active_port;//0：所有端口都选通，1~8，实际对应的1~8端口
wire		mem_read_start;

wire		chip_dmx_ack;
wire		badpoint_req,badpoint_ready,badpoint_end;
wire	[7:0]	badpoint_addr,badpoint_data;
wire		err_ack_flag,err_ack_data,err_ack_type;
wire	[15:0]	bad_p_max;

wire		dmx_rec_end;
wire	[7:0]	dmx_buf_raddr;
wire		dmx_mem_active,fpga_sta_active;

wire	[4:0]	dmx_ack_waddr,dmx_ack_raddr;
wire	[7:0]	dmx_ack_wdata,dmx_ack_rdata;
wire		dmx_ack_wen;

/////////mcu-fpga/////////////////////
wire		spi_rec_flag;
wire	[7:0]	spi_rec_data;
wire		spi_rec_error;
wire	[1:0]	spi_rec_vendor;

wire		spi_send_flag;
wire		spi_send_pre;
wire	[7:0]	spi_send_data;

wire		com2_op_start_flag,com2_rec_flag,com2_rec_end,com2_send_flag,com2_send_end,com2_send_buf_we;
wire	[7:0]	com2_op_length;
wire	[31:0]	com2_op_start_addr;
wire	[7:0]	com2_rec_buf_raddr,com2_rec_buf_rdata,com2_send_buf_waddr,com2_send_buf_wdata;

wire		mcu_rec_end,mcu_send_end,mcu_buf_we;
wire	[7:0]	mcu_buf_raddr,mcu_buf_waddr,mcu_buf_wdata;
wire		cmd_d_ok;
wire	[19:0]	cmd_addr;
wire	[7:0]	cmd_data;

wire	[7:0]	mcu_state_addr,mcu_state_data;
wire		mcu_state_active,mcu_offline_active;
//////////////////////////////////////
//程序版本信息

parameter	SUB	=0;	   //分控
parameter	ASSIST	=1;	   //附属设备

parameter	ACTIVE	=1;
parameter	TEST	=2;	   
parameter	INIT	=3; 

//需要修改部分 start
parameter	MAIN_FUNCTION	=  8'h53;   //ASCII "S"  
parameter	SUB_FUNCTION	=  8'h4C;   //ASCII "L"  
parameter	MAIN_FSOLUTION	=  8'd9;    //"9"        
parameter	SUB_SOLUTION	=  8'd9;    //"08"       
parameter	APPLICATION_TYPE=  8'h4E;   //ASCII "n"  
parameter	MAIN_VERSION	=  8'd1;    //"02"       
parameter	SUB_VERSION	=  8'd6;   //X" 01"  

parameter	MODE    =INIT;//active, test, init

parameter	INIT_ADDR	=14'b0000_0000_1100_00;//0x00C0_0000~0x00C3_FFFF
parameter	TEST_ADDR	=14'b0000_0000_1100_01;//0x00C4_0000~0x00C7_FFFF
parameter	ACT_ADDR	=14'b0000_0000_1100_10;//0x00C8_0000~0x00CB_FFFF

defparam        com_ctrl.DEVICE_TYPE     	=SUB;   //sub,assist
defparam        cascade_ctrl_a.DEVICE_TYPE   	=SUB;   //sub,assist
defparam        cascade_ctrl_b.DEVICE_TYPE   	=SUB; 	//sub,assist
defparam        mcu_com_ctrl.DEVICE_TYPE     	=ASSIST;//sub,assist 

//需要修改部分 end

defparam	mcu_state.LOGIC_MODE		=MODE;
defparam	reboot_ctrl.LOGIC_MODE		=MODE;

defparam	com_ctrl.INITIAL_ADDR		=INIT_ADDR;
defparam 	com_ctrl.TEST_ADDR		=TEST_ADDR;
defparam  	com_ctrl.ACTIVE_ADDR		=ACT_ADDR;

defparam	mcu_com_ctrl.INITIAL_ADDR	=INIT_ADDR;
defparam 	mcu_com_ctrl.TEST_ADDR		=TEST_ADDR;
defparam  	mcu_com_ctrl.ACTIVE_ADDR	=ACT_ADDR;

defparam        state_ctrl_01.main_function   =	MAIN_FUNCTION;
defparam        state_ctrl_01.sub_function    =	SUB_FUNCTION;
defparam        state_ctrl_01.main_solution   =	MAIN_FSOLUTION;
defparam        state_ctrl_01.sub_solution    =	SUB_SOLUTION;
defparam        state_ctrl_01.application_type=	APPLICATION_TYPE;
defparam        state_ctrl_01.main_version    =	MAIN_VERSION;
defparam        state_ctrl_01.sub_version     =	SUB_VERSION;

defparam        mcu_state.main_function   =	MAIN_FUNCTION;             
defparam        mcu_state.sub_function    =	SUB_FUNCTION;                 
defparam        mcu_state.main_solution   =	MAIN_FSOLUTION;               
defparam        mcu_state.sub_solution    =	SUB_SOLUTION;                 
defparam        mcu_state.application_type=	APPLICATION_TYPE;             
defparam        mcu_state.main_version    =	MAIN_VERSION;                 
defparam        mcu_state.sub_version     =	SUB_VERSION;               

//对于1型卡 LOGIC 0 =FPGA2PORT LOGIC 1=PROT2FPGA
//对于2型卡 LOGIC 1 ==FPGA2PORT LOGIC 0=PROT2FPGA
//assign          io_dir=(chip_dmx_ack==1)?1:0;//'d0;
//test
assign		port_da=SR1;
assign		port_db=SR2;
assign		scl='d0;
assign		sda='d0;

//**************************************************************
//		时钟复位管理单元
//**************************************************************
wire	clk_150M;
wire	locked;
//in            sclkin,sys_resetb
//out           sclk,tclk,oclk,resetb      

//out           time_1ms_sync,time_1ms

//IBUFG sclk_in_m (.I(sclkin), .O(sclk_in));

//BUFG CLK0_BUFG_INST0 (.I(sclk_in), .O(sclk));

assign	oclk=(Sim_Mode==0)?clk_150M:sclk;
//assign	oclk=sclk;

sys_reset_ctrl sys_reset_ctrl(
        .sclkin(sclkin),
        .resetb(resetb),
        .reset_phy(reset_phy)
        );

detect_pll_unlock detect_pll_unlock(
	.sclk(sclk),
	.resetb(resetb),
	.key_input(key_input),
	.clk_ok_n(clk_ok_n),
	.tx_err_en(tx_err_en),
	.time_1ms_sync(time_1ms_sync),
	.init_end(init_end),
	.pll_reset(pll_reset)
);
//assign  pll_reset=~sys_resetb;

clk_gen	clk_gen_inst (
	//.areset ( 0),//pll_reset ),
	.inclk0 ( sclkin ),
	.c0 ( sclk ),//sclk
	.c1 ( clk_25M ),
	//.c2 ( clk_150M ),
	//.c3(sa_clk),
	.locked ( locked )
	);
	
clk_gen2        clk_gen_inst_2 (
                .areset ( pll_reset ),
                .inclk0 ( sclk ),
                .c0 ( clk_150M ),
                .c1(sa_clk),
                .locked (  )
                );

sys_timer       sys_timer(
                .resetb(resetb),
                .sclk(sclk),
                
                .time_1us(t_us),
                .time_1ms(time_1ms),
                .time_125ms(time_125ms),
                .time_250ms(time_250ms),
                .time_1s(t_s),
                
                .time_1ms_sync(time_1ms_sync),
                .time_16us_sync(time_16us_sync),
                .time_15ms_sync(time_15ms_sync),
                .time_125ms_sync(time_125ms_sync),
                .time_250ms_sync(time_250ms_sync),
                .time_1s_sync(time_1s_sync)   
                );
                
assign	t_ms = time_1ms;
                
//**************************************************************/
//               面板接口
//**************************************************************/   
assign  key_input=press&cpanel_key;
assign  cpanel_r = led_r;
assign  cpanel_g = inner_led_g;

//**************************************************************
//			整体控制
//**************************************************************
//in            init_end,fpga_rec_flag,op_start_flag,op_start_addr,
//out           init_mode,reboot_en,comm_en

//in            reboot_en

//in            rec_flag,rec_error;
//out           resetb,led_g,led_r,flash_ms,time_1ms  

//分控整体状态控制
s8_main_ctrl_01 main_ctrl(
		.resetb(resetb),
		.sclk(sclk),
		
		.init_end(init_end),
	        .input_active(1'b1),
		.key_active(1'b0),

		.fpga_rec_flag(fpga_rec_flag),
		.op_start_flag(op_start_flag),
		.op_start_addr(op_start_addr),
		
		//模式控制
	        .init_mode(init_mode),
//	        .test_mode(),
		.reboot_en(reboot_en_fpga),
		.comm_en(comm_en),

		.tout(m_tout)
		);
		
//reboot
//icap_ctrl icap_ctrl(
		//.clk(sclk),
//		.rstn(resetb),
//		
//		.start_addr(24'h400000),
//		.addr_preload(1'b0),		//1: multi-boot address will preload during generating bit file
		//.start(reboot_en)
//		.busy()
   		//);
   
wire	[23:0]	reboot_addr;
reboot_ctrl reboot_ctrl(
		.sclk(sclk),
		.resetb(resetb),
		
	        .cmd_d_ok(cmd_d_ok),
	        .cmd_addr(cmd_addr),
	        .cmd_data(cmd_data),
	        
		.reboot_en_fpga(reboot_en_fpga),
		.reboot_addr(reboot_addr),
		.reboot_en(reboot_en),
	);
		
/*active reboot
remote_sys remote_sys(
        .sclk(sclk),
        .reboot_en(reboot_en_mcu | reboot_en_fpga)
);
*/

//init reboot
remote_sys	remote_sys(
//		.sclk(sclk),//clk_50M),
		.clk_25M(clk_25M),
		.resetb(resetb),
		.start(reboot_en),//延迟处理(start),
		.reboot_addr(reboot_addr),
		.busy(busy)
);

//always@(posedge sclk)
//        if(correct_type!=8'hA5)
//                testmode_ini_err<=1'b1;
//        else
//                testmode_ini_err<=1'b0;

//led状态指示
Led_Ctrl_SV2	Led_Ctrl_SV2(
		.resetb(resetb),
		.sclk(sclk),
		
		.time_ms(time_1ms),
                .time_250ms(time_125ms),//time_250ms),

		.G_black(0),
		.G_flash(rec_flag),//(testmode_ini_err&rec_flag),

		.R_light(black_mark),
		.R_flash(rec_error_sync),

		.G_flash_1st(1'd1),
		.R_flash_1st(1'd0),
		
		.tx_err_en(tx_err_en),
		
		.nG_led(inner_led_g),
		.nR_led(led_r)
		);


ledG_press_IO ledG_press_IO(
                .sclk(sclk),
                .input_active(input_active),
                .detect_sync(time_15ms_sync),
                .sample_sync(time_1ms_sync),
                
                .inner_led_g(inner_led_g),
                .led_g(led_g),
                .key_in(key_in),
                .press(press)                
                );

//**************************************************************
//		   千兆级联模块
//**************************************************************    
//in    千兆A/B口输入信号
//out   千兆A/B口输出信号

//in    send_flag,pre_flag,send_data,flash_ms
//out   rec_flag,rec_data,rec_error,input_active  

                    
RGMII_rec_io rec_io_a(
		.rst(~resetb),

		.rxc(gp0_rxc),
		.rxdv(gp0_rxdv),
		.rxd(gp0_rxd),		
			
		.rx_clk(gp0_rx_clk),
		.rx_dv(gp0_rx_dv),
		.rx_data(gp0_rx_data),

		.rx_er(),
		.rx_crs(),
		.rx_col()
		);
assign gp0_tx_clk=(gp0_rx_type==2)?clk_25M:sclk;
RGMII_trans_io trans_io_a(
		.rst(~resetb),

		.tx_clk(gp0_tx_clk),
		.tx_en(gp0_tx_en),
		.tx_data(gp0_tx_data),

		.tclk(gp0_tx_clk),//tclk),

		.txc(gp0_txc),
		.txen(gp0_txen),
		.txd(gp0_txd)		
		);

RGMII_rec_io rec_io_b(
		.rst(~resetb),

		.rxc(gp1_rxc),
		.rxdv(gp1_rxdv),
		.rxd(gp1_rxd),		
			
		.rx_clk(gp1_rx_clk),
		.rx_dv(gp1_rx_dv),
		.rx_data(gp1_rx_data),

		.rx_er(),
		.rx_crs(),
		.rx_col()
		);
assign gp1_tx_clk=(gp1_rx_type==2)?clk_25M:sclk;
//assign	gp1_rx_dv=0;	//测试用
//assign	gp1_rx_data=0;	//测试用

RGMII_trans_io trans_io_b(
		.rst(~resetb),

		.tx_clk(gp1_tx_clk),
		.tx_en(gp1_tx_en),
		.tx_data(gp1_tx_data),
//		.tx_en(0),	//测试用
//		.tx_data(0),	//测试用

		.tclk(gp1_tx_clk),//tclk),

		.txc(gp1_txc),
		.txen(gp1_txen),
		.txd(gp1_txd)
		);

v8_cascade_ctrl_01 cascade_ctrl_a(
		.resetb(resetb),
		.sclk(sclk),

		.rx_clk(gp0_rx_clk),
		.rx_dv(gp0_rx_dv),
		.rgmii_rx_data(gp0_rx_data),
		.rx_type(gp0_rx_type),
		
		.rec_flag(gp0_rec_flag),
		.rec_data(gp0_rec_data),
		.rec_error(gp0_rec_error),
		.blank_flag(gp0_blank_flag),

		.i_tx_en(gp1_send_flag),
		.i_tx_pre(gp1_pre_flag),
		.i_tx_data(gp1_send_data),
		
		.tx_clk(gp1_tx_clk),
		.tx_en(gp1_tx_en),
		.tx_data(gp1_tx_data),
		.tx_type(gp1_rx_type),
		.tx_err_en(tx_err_en),

		.tout()
		);

v8_cascade_ctrl_01 cascade_ctrl_b(
		.resetb(resetb),
		.sclk(sclk),

		.rx_clk(gp1_rx_clk),
		.rx_dv(gp1_rx_dv),
		.rgmii_rx_data(gp1_rx_data),
		.rx_type(gp1_rx_type),
//		.rx_clk(0),
//		.rx_dv(0),
//		.rx_data(0),
		
		.rec_flag(gp1_rec_flag),
		.rec_data(gp1_rec_data),
		.rec_error(gp1_rec_error),
		.blank_flag(gp1_blank_flag),

		.i_tx_en(gp0_send_flag),
		.i_tx_pre(gp0_pre_flag),
		.i_tx_data(gp0_send_data),
		
		.tx_clk(gp0_tx_clk),
		.tx_en(gp0_tx_en),
		.tx_data(gp0_tx_data),
		.tx_type(gp0_rx_type),
                .tx_err_en(tx_err_en),

		.tout()
		);

//端口选择
v8_port_select_01 port_select(
		.resetb(resetb),
		.sclk(sclk),
		
		.flash_ms(time_1ms),
                .time_125ms(time_125ms),

		.gp0_rec_flag(gp0_rec_flag),
		.gp0_rec_data(gp0_rec_data),
		.gp0_rec_error(gp0_rec_error),
		.gp0_blank_flag(gp0_blank_flag),
		
		.gp1_rec_flag(gp1_rec_flag),
		.gp1_rec_data(gp1_rec_data),
		.gp1_rec_error(gp1_rec_error),
		.gp1_blank_flag(gp1_blank_flag),
		
		.rec_flag(rec_flag),
		.rec_data(rec_data),
		.rec_error(rec_error),
		.rec_vendor(rec_vendor),
		.rec_error_sync(rec_error_sync),
		.yt_vs_pre(yt_vs_pre),
		
		.send_flag(send_flag),
		.pre_flag(pre_flag),
		.send_data(send_data),
		
		.blank_flag(blank_flag),
		.redu_flag(redu_flag),
		
		.gp0_send_flag(gp0_send_flag),
		.gp0_pre_flag(gp0_pre_flag),
		.gp0_send_data(gp0_send_data),
		
		.gp1_send_flag(gp1_send_flag),
		.gp1_pre_flag(gp1_pre_flag),
		.gp1_send_data(gp1_send_data),
		
		.input_active(input_active),
		
		.tout()
		);

//测试用
//assign	rec_flag=gp0_rec_flag;
//assign	rec_data=gp0_rec_data;
//assign	rec_error=gp0_rec_error;
		
//**************************************************************
//		通讯数据处理/上电初始化
//**************************************************************        
//in    rec_flag、rec_data、rec_error
//out   send_flag、pre_flag、send_data       
//out   set_d_ok、set_addr、set_data
//out   init_correct_d_ok、init_correct_addr、init_correct_data
//out   init_mode、init_end

//in/out   FLASH接口

//in    comm_en,init_mode
//out   init_end
                    
v8_com_ctrl_01 com_ctrl(
		.resetb(resetb),
		.sclk(sclk),
		.comm_en(comm_en),

		.rec_flag(rec_flag),
		.rec_error(rec_error),
		.rec_data(rec_data),
		.rec_vendor(rec_vendor),
		
		.send_flag(send_flag),
		.pre_flag(pre_flag),
		.send_data(send_data),
		
		.blank_flag(blank_flag),
		.redu_flag(redu_flag),
		.time_1ms_sync(time_1ms_sync),
		
		.fpga_rec_flag(fpga_rec_flag),
		.fpga_send_flag(fpga_send_flag),
		.op_start_flag(op_start_flag),
		.op_start_addr(op_start_addr),
		.op_length(op_length),

		.fpga_rec_end(fpga_rec_end),	
		.rec_buf_raddr(rec_buf_raddr),
		.rec_buf_rdata(rec_buf_rdata),		

		.fpga_send_end(fpga_send_end),	
		.send_buf_we(send_buf_we),
		.send_buf_waddr(send_buf_waddr),
		.send_buf_wdata(send_buf_wdata),	
		
		.tout()
		);

v8_com_bus_01 com_bus(
		.resetb(resetb),
		.sclk(sclk),

		//和com_ctrl接口
		.fpga_rec_flag(fpga_rec_flag),
		.fpga_send_flag(fpga_send_flag),
		.op_start_flag(op_start_flag),
		.op_start_addr(op_start_addr),

		.fpga_rec_end(fpga_rec_end),
		.rec_buf_raddr(rec_buf_raddr),

		.fpga_send_end(fpga_send_end),
		.send_buf_we(send_buf_we),
		.send_buf_waddr(send_buf_waddr),
		.send_buf_wdata(send_buf_wdata),	

		//和flash_ctrl接口
		.flash_rec_end(flash_rec_end),
		.flash_buf_raddr(flash_buf_raddr),

		.flash_send_end(flash_send_end),
		.flash_buf_we(flash_buf_we),
		.flash_buf_waddr(flash_buf_waddr),
		.flash_buf_wdata(flash_buf_wdata),	

		//和display_ctrl接口
		.display_rec_end(display_rec_end),
		.display_buf_raddr(display_buf_raddr),

		.display_send_end(display_send_end),
		.display_buf_we(display_buf_we),
		.display_buf_waddr(display_buf_waddr),
		.display_buf_wdata(display_buf_wdata),	

		//和output ctrl接口
		.mcu_rec_end(dmx_rec_end),
		.mcu_buf_raddr(dmx_buf_raddr),
		
		.tout()
		);


//flash控制  
                
v8_flash_ctrl_02 flash_ctrl(
		.resetb(resetb),
		.sclk(sclk),

		//和通讯模块接口
		.fpga_rec_flag(fpga_rec_flag),
		.fpga_send_flag(fpga_send_flag),
		.op_start_flag(op_start_flag),
		.op_start_addr(op_start_addr),
		.op_length(op_length),

		.rec_end(flash_rec_end),
		.rec_buf_raddr(flash_buf_raddr),
		.rec_buf_rdata(rec_buf_rdata),		

		.send_end(flash_send_end),
		.send_buf_we(flash_buf_we),
		.send_buf_waddr(flash_buf_waddr),
		.send_buf_wdata(flash_buf_wdata),	

		//和显示模块接口
		.read_start(read_start),
		.start_addr(start_addr),
		.read_end(read_end),
                .cc_128_16(cc_128_16), 
                		
		.read_d_ok(read_d_ok),
		.read_data(read_data),

		//和flash接口
	        .flash_SO(flash_SO),
		.flash_SCK(flash_SCK),
		.flash_SI(flash_SI),
		.flash_CS_n(flash_CS_n),

        	.tout()
		);

epcs_io epcs_io(
	.asdo_in(flash_SI),
	.asmi_access_granted(1'b1),
	.dclk_in(flash_SCK),
	.ncso_in(flash_CS_n),
	.noe_in(1'b0),
	.asmi_access_request(),
	.data0_out(flash_SO));
                    
//显示设置接口
display_bus_01 display_bus(
		.resetb(resetb),
		.sclk(sclk),
                
                .cc_96_16(1'b1),  
                .cc_128_16(1'b0), 
                .cc_256_16(1'b0),
                .lc_256_8(1'b0),                

		//和主控模块接口
		.init_mode(init_mode),
		.init_end(init_end),
		
		//和通讯模块接口
		.fpga_rec_flag(fpga_rec_flag),
		.fpga_send_flag(fpga_send_flag),
		.op_start_flag(op_start_flag),
		.op_start_addr(op_start_addr),
		.op_length(op_length),

		.rec_end(display_rec_end),
		.rec_buf_raddr(display_buf_raddr),
		.rec_buf_rdata(rec_buf_rdata),		

		.send_end(display_send_end),
		.send_buf_we(display_buf_we),
		.send_buf_waddr(display_buf_waddr),
		.send_buf_wdata(display_buf_wdata),	

		//和flash模块接口
		.read_start(read_start),
		.start_addr(start_addr),
		.read_end(read_end),
		
		.read_d_ok(read_d_ok),
		.read_data(read_data),

		//给显示逻辑的参数设置
	        .set_d_ok(set_d_ok),
	        .set_addr(set_addr),
	        .set_data(set_data),
		
		//逐点调整数据
		.init_correct_d_ok(init_correct_d_ok),
	        //.init_correct_addr(init_correct_addr),
	        .init_correct_data(init_correct_data),
	        .load_adj_flag(load_adj_flag),
	        .load_picture_flag(load_picture_flag),	        
		//和显示逻辑的状态读取
		.mcu_mem_active(dmx_mem_active),
		.fpga_sta_active(fpga_sta_active),
	        .state_addr(state_addr),
	       // .state_data(state_data),
	        .mcu_state_data(dmx_state_data),
	        .fpga_state_data(fpga_state_data),
	        .bd_state_data(bd_state_data),
//	        .state_data(0),

		.badpoint_req(badpoint_req),		//读BUF请求
		.badpoint_ready(badpoint_ready),	//开始可以读buf的标志
		.badpoint_addr(badpoint_addr),		//读地址
		.badpoint_data(badpoint_data),		//读数据
		.badpoint_end(badpoint_end),		//读结束标志
		
 		.read_eep_en(read_eep_en),
                .read_eep_addr(read_eep_addr),
                .eep_d_ok(eep_d_ok),
                .eep_data(eep_data),
        	.tout(disp_tout)
		);

//状态寄存器
state_ctrl_02	state_ctrl_01(
		.resetb(resetb),
        	.sclk(sclk),

		//千兆PHY接口
		.rec_flag(rec_flag),
		.rec_error(rec_error),
		        
		//和通讯模块接口
		.set_addr(set_addr),
		.set_d_ok(set_d_ok),
		.set_data(set_data),
//		.bad_p_max(bad_p_max),	
		.dmx_ack_raddr(dmx_ack_raddr),
		.dmx_ack_rdata(dmx_ack_rdata),	
		//状态寄存器
		.fpga_sta_active(fpga_sta_active),
		.state_addr(state_addr),
		.state_data(fpga_state_data),
		.fpga_rec_flag(fpga_rec_flag),
		
		//输出给led灯和输出控制模块
		.black_mark(black_mark)
		);

dmx_ack dmx_ack(
		.sclk(sclk),
		.resetb(resetb),
		
		//输出控制模块接口
		.mem_err_sel(mem_err_sel),
        	.clk_sel(clk_sel),
        	.err_port_num(err_port_num),
        	.err_read_start	(err_read_start),
        	.mem_active_port(mem_active_port),
        	.mem_read_start	(mem_read_start),
		
		.t_us(t_us),
	
		//返回数据
		.dmx_ack_in(dmx_ack_in),
		//状态寄存器的总坏点数接口
//		.bad_p_max(bad_p_max),

		.dmx_ack_waddr(dmx_ack_waddr),
		.dmx_ack_wdata(dmx_ack_wdata),
		.dmx_ack_wen(dmx_ack_wen),

			
		.mcu_mem_active(dmx_mem_active),
		.state_addr(state_addr),
		.state_data(dmx_state_data),
		
		//通讯读接口
		.r_req(badpoint_req),		//读BUF请求
		.r_ready(badpoint_ready),	//开始可以读buf的标志,1个clk
		.r_addr(badpoint_addr),		//读地址
		.r_data(badpoint_data),		//读数据
		.r_end(badpoint_end)		//读结束标志
		);
				
box_detect      box_detect(
                .sclk(sclk),
                .resetb(resetb),
                
                .bd_clk(bd_clk),
                .bd_din(bd_din),
                .bd_dout(bd_dout),
                .bd_en(bd_en),
                
                .state_addr(state_addr),
                .state_data(bd_state_data),
                                
                .read_eep_en(1'b0),
                .read_eep_addr(read_eep_addr),
                .eep_d_ok(eep_d_ok),
                .eep_data(eep_data),

                .bd_wdata(bd_wdata),
                .bd_wen(bd_wen),
                .bd_waddr(bd_waddr),                  
                .bd_raddr(bd_raddr),
                .bd_rdata(bd_rdata),
                
                .set_state_ini(set_state_ini),
                .set_state_ini_addr(set_state_ini_addr),
                .set_state_ini_data(set_state_ini_data)  
                );

//**************************************************************
//		MCU与FPGA接口
//**************************************************************
mcu_interface_02 mcu_interface(
			.sclk(sclk),
			.resetb(resetb),
			
			.spi2_cs(spi2_cs),
			.spi2_mosi(spi2_mosi),
			.spi2_miso(spi2_miso),
			.spi2_clk(spi2_clk),
			
			.spi_rec_flag(spi_rec_flag),
			.spi_rec_data(spi_rec_data),
			.spi_rec_error(spi_rec_error),
			.spi_rec_vendor(spi_rec_vendor),
			
			.spi_send_flag(spi_send_flag),
			.spi_send_pre(spi_send_pre),
			.spi_send_data(spi_send_data),
			
			.tout()
				);

mcu_com_ctrl_01 mcu_com_ctrl(
		.resetb(resetb),
		.sclk(sclk),
		.comm_en(1),
                
		.rec_flag(spi_rec_flag),
		.rec_error(spi_rec_error),
		.rec_data(spi_rec_data),
		.rec_vendor(spi_rec_vendor),
		
		.send_flag(spi_send_flag),
		.pre_flag(spi_send_pre),
		.send_data(spi_send_data),
		
		.blank_flag(0),
		.redu_flag(0),
		.time_1ms_sync(time_1ms_sync),
		
		.fpga_rec_flag(com2_rec_flag),
		.fpga_send_flag(com2_send_flag),
		.op_start_flag(com2_op_start_flag),
		.op_start_addr(com2_op_start_addr),
		.op_length(com2_op_length),
                
		.fpga_rec_end(com2_rec_end),	
		.rec_buf_raddr(com2_rec_buf_raddr),
		.rec_buf_rdata(com2_rec_buf_rdata),		
                
		.fpga_send_end(com2_send_end),	
		.send_buf_we(com2_send_buf_we),
		.send_buf_waddr(com2_send_buf_waddr),
		.send_buf_wdata(com2_send_buf_wdata),	
                
		.tout()
		);

mcu_com_bus_01 mcu_com_bus(
		.resetb(resetb),
		.sclk(sclk),

		//和com_ctrl接口
		.fpga_rec_flag(com2_rec_flag),
		.fpga_send_flag(com2_send_flag),
		.op_start_flag(com2_op_start_flag),
		.op_start_addr(com2_op_start_addr),

		.fpga_rec_end(com2_rec_end),
		.rec_buf_raddr(com2_rec_buf_raddr),

		.fpga_send_end(com2_send_end),
		.send_buf_we(com2_send_buf_we),
		.send_buf_waddr(com2_send_buf_waddr),
		.send_buf_wdata(com2_send_buf_wdata),	

		//和mcu_ctrl接口
		.mcu_rec_end(mcu_rec_end),
		.mcu_buf_raddr(mcu_buf_raddr),
               
		.mcu_send_end(mcu_send_end),
		.mcu_buf_we(mcu_buf_we),
		.mcu_buf_waddr(mcu_buf_waddr),
		.mcu_buf_wdata(mcu_buf_wdata),	
		
		.tout()
		);
		
//显示设置接口
mcu_data_bus_01 mcu_data_bus(
		.resetb(resetb),
		.sclk(sclk),
                            
		//和主控模块接口
		.init_mode(0),
		
		//和通讯模块接口
		.fpga_rec_flag(com2_rec_flag),
		.fpga_send_flag(com2_send_flag),
		.op_start_flag(com2_op_start_flag),
		.op_start_addr(com2_op_start_addr),
		.op_length(com2_op_length),

		.rec_end(mcu_rec_end),
		.rec_buf_raddr(mcu_buf_raddr),
		.rec_buf_rdata(com2_rec_buf_rdata),		

		.send_end(mcu_send_end),
		.send_buf_we(mcu_buf_we),
		.send_buf_waddr(mcu_buf_waddr),
		.send_buf_wdata(mcu_buf_wdata),	


		//给MCU相关控制逻辑的接口设置
	        .cmd_d_ok(cmd_d_ok),
	        .cmd_addr(cmd_addr),
	        .cmd_data(cmd_data),
		       
		//读参数设置
		.mcu_offline_active(mcu_offline_active),
		.mcu_state_active(mcu_state_active),
	        .mcu_state_addr(mcu_state_addr),
	        .mcu_state_data(mcu_state_data),

        	.tout()
		);	
//状态寄存器
mcu_state_01	mcu_state(
		.resetb(resetb),
        	.sclk(sclk),
        	
		//写参数接口
	        .cmd_d_ok(cmd_d_ok),
	        .cmd_addr(cmd_addr),
	        .cmd_data(cmd_data),
	        
	        //读参数接口
		.mcu_state_active(mcu_state_active),
		.mcu_offline_active(mcu_offline_active),
		.mcu_state_addr(mcu_state_addr),
		.mcu_state_data(mcu_state_data),        
		
		.phy_result(),
		.hub_result(),
		.sdram_result(),
		
		//寄存器
		.sd_card_vaild(),
		.reboot_en_mcu(reboot_en_mcu),
		//.sd_swp(sd_swp),
		.offline_vs_en()

		);
                            
//**************************************************************
//		  显示数据处理
//************************************************************** 
//in    set_d_ok,set_addr,set_data
//in    rec_flag,rec_data
//
//in    out_clk,r_frame_sync、scan_num、bit_num、unit_num、buf_sel、obuf_raddr
//out   obuf_rdata
//in/out   SDRAM接口      

v8_data_rec_02 data_rec(
		.resetb(resetb),
		.sclk(sclk),
		
	        .set_d_ok(set_d_ok),
	        .set_addr(set_addr),
	        .set_data(set_data),

		.init_mode(init_mode),
		.black(black),
		.test_vs(vs_a),
		.local_test_en(local_test_en),
		.local_picture_en(local_picture_en),        

                .pixel_mode(pixel_mode),

		.mac_flag(rec_flag),
		.mac_data(rec_data),
		.mac_vendor(rec_vendor),
		.mac_error(rec_error),
		.yt_vs_pre(yt_vs_pre),
				
		.vsout(vs),
		.hsout(hs),
		.dout(data),

		.h_num(h_num),
                .h_total_reg(h_total_reg),
                .l_total_reg(l_total_reg),
		.h_total(h_total),
                .l_total(l_total),
                
		.state(state),	
		.state_2(state_2),

		.unit_color_addr(unit_color_addr),
		.unit_color_adj(unit_color_adj),
		.unit_color_valid(unit_color_valid),
                .cascade_light(cascade_light),

		.no_vs_set(no_vs_set),                
                
		.tout()
		);

//按键测试

button_debounce button(
		.resetb(resetb),
		.sclk(sclk),
		.a_second(time_250ms_sync),
		.press(key_input),
		.press_detect(press_detect)
		);
		
test_out_01 test_out(
		.resetb(resetb),
		.sclk(sclk),
                
                .no_vs_set(no_vs_set), 
		.input_active(input_active),
		.press_detect(press_detect),
		.frame_flag(time_15ms_sync),
		.a_second(time_1s_sync),
		.pixel_mode(pixel_mode),
		.vir_disp(state[7]),
		
		.h_max(h_total),
                .l_max(l_total),
		
		.vsin(vs),
		.h_num_in(h_num),
		.hsin(hs),
		.din(data),
		
		.local_test_en(local_test_en),
		.local_picture_en(local_picture_en),
		
		.vsout(vs_a),
		.h_num_out(h_num_a),
		.hsout(hs_a),
		.dout(data_a),
		
		.v_start(v_start)
		);
	
		
//灰度数据处理
s8_gray_light gray_light(
		.resetb(resetb),
		.sclk(sclk),
		
	        .set_d_ok(set_d_ok),
	        .set_addr(set_addr),
	        .set_data(set_data),	
	        
	        .local_picture_en(local_picture_en),
	        .unit_type(unit_type),
                .pixel_mode(pixel_mode), 	
                .unit_pixel_w_max(unit_pixel_w_max),
                .RVport_mode(RVport_mode),
                .l_total_reg(l_total_reg),
                .h_total_reg(h_total_reg),
                .mode_port_free(mode_port_free),
                .empty_right(empty_right),
                .empty_down(empty_down),      	
                .port_20_en(port_20_en),
                .port_24_en(port_24_en),  
                .data_inv_en(data_inv_en),              
		.state(state),	
		.correct_type(correct_type),
		
		.v_start(v_start),
		.hsin(hs_a),
		.din(data_a),
		.h_num(h_num_a),
		
   		.adj_h_start(adj_h_start),
   		.adj_rd_start2(adj_rd_start2),
   		.adj_h_num(adj_h_num),
   		.adj_read_end(adj_read_end),
		.adjust_addr(adjust_addr),
		.adjust_data(adjust_data),
//   		.adj_read_end(adj_h_start),	//测试用
//		.adjust_data(8'hff),		//测试用
		
//		.unit_color_addr(unit_color_addr),
		.unit_color_adj(unit_color_adj),

		.hsout(hs_b),
		.dout(data_b),
		.h_num_out(h_num_b),		
		.cycle_max(cycle_max),		
		.h_start(h_b_start),
		.h_end(h_b_end),
                .l_total_reg_out(l_total_reg_b),
                .cc_96_16(cc_96_16),  
                .cc_128_16(cc_128_16), 
                .cc_256_16(cc_256_16),
                .lc_256_8(lc_256_8),  

		.info_addr(info_addr),		
		.info_data(info_data),		

		.tout(g_tout)
		);

//**************************************************************
//         显示数据存储与读取
//************************************************************** 
wire		disp_read_req;
wire	[23:0]	disp_read_addr;
wire	[3:0]	disp_read_cnt;
wire            disp_read_ack;
wire    [31:0]  disp_read_data;

wire 	[15:0]	out_data;
wire 	[15:0]	out_data_n;
wire            clk_out;
wire            clk_out_n;

/* initial去掉
defparam	sdram_top.Sim_Mode	=Sim_Mode;


s8_sdram_top_01 sdram_top(
        .resetb(resetb),
        .sclk(sclk),

        .init_mode(init_mode),
        .set_addr(set_addr),	
	.set_data(set_data),
	.set_d_ok(set_d_ok),
	
        .sync_16_us(time_16us_sync),
        
        .v_start(v_start),
        .state(state),    
        .hsin(hs_a),
        .din(data_a),
        .h_num(h_num_a),
        
//        .unit_color_addr(unit_color_addr),
//        .unit_color_adj(16'h0100),//unit_color_adj),
        
        .read_req (disp_read_req),
        .read_addr(disp_read_addr),
        .read_cnt(disp_read_cnt),
        .read_ack (disp_read_ack),
        .read_data(disp_read_data),

        .sa_clk(),
        .sa_cnt(sa_cnt),
        .sa_addr(sa_addr),
        .sa_bank(sa_bank),
        .sa_data(sa_data),
        
        .tout()
        );

*/
assign        sa_dqm_l=0;
assign        sa_dqm_h=0;

//**************************************************************
//		        输出控制
//************************************************************** 
//in    input_active,no_vs_set,comm_en
//in    set_d_ok,set_addr,set_data
//
//out   out_clk, r_frame_sync、scan_num、bit_num、unit_num、buf_sel、obuf_raddr
//in    obuf_rdata

//out   显示输出接口

//黑屏控制
black_ctrl      black_ctrl(
                .resetb(resetb),
                .sclk(sclk),
                
                .time_125ms_sync(time_125ms_sync),
                .init_mode(init_mode),
                .input_active(input_active),
                .local_test_en(local_test_en),
                
                .black_mark(black_mark),                  
                .state(state), 
                .no_vs_set(no_vs_set),
                
                .black(black)
                );  

/* initial去掉
//灯饰输出控制模块
defparam	out_ctrl_lamp.Sim_Mode = Sim_Mode;

out_ctrl_lamp out_ctrl_lamp(
        .resetb			(resetb),
        .sclk			(sclk),
	.oclk			(oclk),
        
        .set_d_ok		(set_d_ok),
        .set_addr		(set_addr),
        .set_data		(set_data),
        
        .init_correct_d_ok	(init_correct_d_ok),
        .init_correct_addr	(init_correct_addr),
        .init_correct_data	(init_correct_data),
        
        .t_us			(t_us),
        .t_ms			(t_ms),
        .t_s			(t_s),

        .out_en			(comm_en),
        .v_start		(v_start),
        .black			(black),
        .state_2		(state_2),
        
        .unit_color_addr	(unit_color_addr),
	.unit_color_adj		(unit_color_adj),
	.unit_color_valid	(unit_color_valid),

        .disp_read_req		(disp_read_req),
        .disp_read_addr		(disp_read_addr),
        .disp_read_cnt		(disp_read_cnt),
        .disp_read_ack		(disp_read_ack),
        .disp_read_data		(disp_read_data),
               
        .out_sync		(out_sync),
        .out_data		(out_data),
        .out_data_n		(out_data_n),
        .clk_out		(clk_out),
        .clk_out_n		(clk_out_n),
 
	.mem_err_sel		(mem_err_sel),
        .clk_sel		(clk_sel),
        .err_port_num		(err_port_num),
        .err_read_start		(err_read_start),
        .mem_active_port	(mem_active_port),
        .mem_read_start		(mem_read_start),

        .chip_dmx_ack		(chip_dmx_ack),

	.op_start_flag		(op_start_flag),
	.fpga_rec_flag		(fpga_rec_flag),
	.op_start_addr		(op_start_addr),
	
	.rec_end		(dmx_rec_end),
	.rec_buf_raddr		(dmx_buf_raddr),
	.rec_buf_rdata		(rec_buf_rdata),
     
        .tout			(out_tout)     
	);

*/
mix_sram   mix_sram(        
                .resetb(resetb),
                .sclk(sclk),
                
                .init_mode(init_mode),
                
		.set_addr(set_addr),		//添加的接口
		.set_data(set_data),
		.set_d_ok(set_d_ok),

		.dmx_ack_waddr(dmx_ack_waddr),
		.dmx_ack_wdata(dmx_ack_wdata),
		.dmx_ack_wen(dmx_ack_wen),
		.dmx_ack_raddr(dmx_ack_raddr),
		.dmx_ack_rdata(dmx_ack_rdata),
		
                .bd_wdata(bd_wdata),
                .bd_wen(bd_wen),
                .bd_waddr(bd_waddr),                  
                .bd_raddr(bd_raddr),
                .bd_rdata(bd_rdata),   
                
                .unit_num(table_unit_num),
                .unit_table_dout(unit_table_dout)
                );

output_select output_select(
                .oclk(oclk),
                .RVport_mode(RVport_mode),
                .unit_type(unit_type),
                .port_20_en(port_20_en),
                .port_24_en(port_24_en),
                .SR_set(SR_set),
                .display_sync(display_sync),
                .vs_a(vs_a),
                .o_sclk(o_sclk),                
                .o_load(o_load),
                .o_loeb(o_loeb),
                .o_data(o_data),
                .o_h_sel(o_h_sel),
                .o_hoeb(o_hoeb),
                .out(out),
                .tout()     
                );



//assign  RV_2=(RVport_mode[3:0]==1)?      1:0;
//assign  RV2_26pin=(RV_2==1 && (RVport_mode[7:4]==1||unit_type[4]==1))? 1:0;

//背板接口           
//assign	fi_oe=1'b1;
//assign	fo_oe=1'b0;  

wire	port_clk,port_oe,port_load;
wire    p1_d,p2_d,p3_d,p4_d,p5_d,p6_d,p7_d,p8_d;
wire    p1_le,p2_le,p3_le,p4_le,p5_le,p6_le,p7_le,p8_le;
wire	ex1,ex2,ex3,ex4,ex5,ex6;
wire	in1,in2,in3,in4,in5,in6,in7,in8;

assign  p1_d=out_data[0];  
assign  p2_d=out_data[1];  
assign  p3_d=out_data[2];  
assign  p4_d=out_data[3];  
assign  p5_d=out_data[4];  
assign  p6_d=out_data[5];  
assign  p7_d=out_data[6];  
assign  p8_d=out_data[7];  

assign  p1_le=out_data_n[0];
assign  p2_le=out_data_n[1];
assign  p3_le=out_data_n[2];
assign  p4_le=out_data_n[3];
assign  p5_le=out_data_n[4];
assign  p6_le=out_data_n[5];
assign  p7_le=out_data_n[6];
assign  p8_le=out_data_n[7];

assign	ex1=1'b0;
assign	ex2=1'b0;
assign	ex3=1'b0;
assign	ex4=1'b0;
assign	ex5=1'b0;
assign	ex6=1'b0;

assign	in1=1'bz;
assign	in2=1'bz;
assign	in3=1'bz;
assign	in4=1'bz;
assign	in5=1'bz;
assign	in6=1'bz;

assign	port_clk	=clk_out;
assign	port_load	=clk_out_n;
assign	port_oe		=clk_out_n;

assign	dmx_ack_in	=(chip_dmx_ack==1)?{portb_data[9],portb_data[10],portb_data[29],portb_data[17],portb_data[28],portb_data[31],portb_data[30],portb_data[19]}:{8'b0};//


assign	portb_h_sel[0]=in2;
assign	portb_load=in4;
assign	portb_clk =in5;
assign 	portb_oe=in6;
assign	porta_clk=in7;
assign	bd_din=in8;

assign	portb_data[31:0]=(chip_dmx_ack==1)?
			{1'bz,1'bz,1'bz,1'bz,2'b0,p1_le,p1_d,p2_le,p2_d,p3_le,p3_d,1'bz,1'b0,1'bz,p4_le,p4_d,p5_le,p6_d,p7_le,p5_d,1'bz,1'bz,1'b0,p8_d,p8_le,in1,in3,1'b0,p6_le,p7_d,1'b0}:
			{port_clk,port_oe,ex4,ex2,2'b0,p1_le,p1_d,p2_le,p2_d,p3_le,p3_d,ex1,1'b0,ex3,p4_le,p4_d,p5_le,p6_d,p7_le,p5_d,ex5,ex6,1'b0,p8_d,p8_le,in1,in3,1'b0,p6_le,p7_d,1'b0};
//assign	porta_clk	=clk_out;
//assign	porta_load	=clk_out_n;
//assign	porta_oe	=clk_out_n;
//
//assign  porta_h_sel	=(chip_dmx_ack==1)?1'bz:{2'b0,led_r,led_g};
////assign  porta_h_sel	={2'b0,led_r,led_g};
////assign	porta_h_sel	={out_sync,led_r,led_g};
//assign	porta_data[31:0]=32'b0;
////assign	porta_data[31:0]={3'b000,p4_le,3'b000,p4_d,3'b000,p3_le,3'b000,p3_d,3'b000,p2_le,3'b000,p2_d,3'b000,p1_le,3'b000,p1_d};
////assign	porta_data[31:0]=disp_read_data;
////assign	porta_data[31:0]={h_num_a,data_a,hs_a,vs_a,v_start,local_test_en,press_detect,input_active};
//assign  SR1             =vs_a;            
//
//               
//assign	portb_clk	=clk_out;
//assign	portb_load	=clk_out_n;
//assign	portb_oe	=clk_out_n;
//
//assign  portb_h_sel	=(chip_dmx_ack==1)?1'bz:{2'b0,led_r,led_g};
////assign  portb_h_sel	={2'b0,led_r,led_g};
////assign	portb_h_sel	={out_sync,led_r,led_g};
//assign	portb_data[31:0]={15'b0,led_g,led_r,p8_le,p8_d,p7_le,p6_le,p7_d,p4_le,p4_d,p6_d,p3_le,p3_d,p2_le,p5_le,p2_d,p1_le,p1_d,p5_d};
////assign	portb_data[31:0]=out_tout;
//assign  SR2             =t_us;

//************************************************************/
//		未用接口
//************************************************************/                    
//测试用信号


//PHY复位控制
//assign	reset_phy=1'b1;
//assign	tout={sd_tout[0],o_tout[0],obuf_rdata[0]};

//***************通讯测试**************
//assign	clk_ok_n=time_250ms;
test_clk test_clk(
	.clkin(clk_150M),
	.sclk(sclk),
	.clk_ok_n(clk_ok_n)
	);

//defparam        mdio_ctrl_02.DELAY_TIME   =  22;   //200ms	复位后开始smi通讯的时间
//defparam        mdio_ctrl_02.DELAY_TIME_1   =  19;   //20ms	SMI完成后到RGMII开始发送的时间，未用
//
//mdio_ctrl_02	mdio_ctrl_02(
//	.sclk(sclkin),
//	.rst_n(resetb),
//	.mdio(mdio),
//	.mdc(mdc),
//	.tx_reset()    //0-1
//);

///////////////////////////////////////
rx_clk_check	rx_clk_check_p0(
	.sclk(sclk),
	.rx_clk(gp0_rx_clk),	
	.clk_type(gp0_rx_type)
	);

rx_clk_check	rx_clk_check_p1(
	.sclk(sclk),
	.rx_clk(gp1_rx_clk),	
	.clk_type(gp1_rx_type)
	);
endmodule

/*历史代码
                
//数据存储
s8_sdram_top_01 sdram_top(
		.resetb(resetb),
		.sclk(sclk),
		.oclk(oclk),

		.init_mode(init_mode),
		.local_picture_en(local_picture_en),
		
	        .set_d_ok(set_d_ok),
	        .set_addr(set_addr),
	        .set_data(set_data),

                .cc_96_16(cc_96_16),  
                .cc_128_16(cc_128_16), 
                .cc_256_16(cc_256_16),
                .lc_256_8(lc_256_8), 
                .l_total_reg(l_total_reg_b),
                .pixel_mode(pixel_mode), 
                .unit_pixel_w_max(unit_pixel_w_max), 
		.unit_l_max(unit_l_max),
		.data_inv_en(data_inv_en),
		.unit_type(unit_type),
		.scan_h_max(scan_h_max), 
                .signal_ctrl(signal_ctrl),
                .shift_length_per_unit(shift_length_per_unit),
                .port_20_en(port_20_en),
                .port_24_en(port_24_en),
                .mode_port_free(mode_port_free),
                .empty_right(empty_right),
                .empty_down(empty_down),
                
	        .adj_d_ok(init_correct_d_ok),
	        .adj_addr(init_correct_addr),
	        .adj_data(init_correct_data),
	        .load_adj_flag(load_adj_flag),
	        .load_picture_flag(load_picture_flag),
	        
		.sync_16_us(time_16us_sync),
		
		.adj_h_start(adj_h_start),
		.adj_rd_start2(adj_rd_start2),
//		.adj_h_start(0),			//测试用
//	        .adj_h_num(adj_h_num),
		.adj_h_num(adj_h_num),
		.adj_read_end(adj_read_end),
		.adjust_addr(adjust_addr),
		.adjust_data(adjust_data),

		.v_start(v_start),
		.state(state),	

		.hsin(hs_b),
		.din(data_b),
		.h_num(h_num_b),		
		.cycle_max(cycle_max),		
		.h_start(h_b_start),
		.h_end(h_b_end),        
                .table_unit_num(table_unit_num),
                .unit_table_dout(unit_table_dout),
                
		.info_addr(info_addr),		
		.info_data(info_data),		
		
		.r_frame_sync(r_frame_sync),
		.scan_num(scan_num),
		.bit_num(bit_num),
		.unit_num(unit_num),
		.color_count(color_count),
		.obuf_sel(obuf_sel),
		.obuf_sync(obuf_sync),
		.obuf_raddr(obuf_raddr),
		.obuf_rdata(obuf_rdata),

		.sa_clk(),
		.sa_cnt(sa_cnt),
		.sa_addr(sa_addr),
		.sa_bank(sa_bank),
		.sa_data(sa_data),

		.tout(sd_tout)
		);

assign		sa_dqm_l=0;
assign		sa_dqm_h=0;


out_cnt_595_D03 out_cnt_595(
		.resetb(resetb),
		.sclk(sclk),
		.oclk(oclk),
		
		.set_d_ok(set_d_ok),
		.set_addr(set_addr),
		.set_data(set_data),

		.work_en(comm_en),

		.black_flag(black),
		.adjust_bit(4'h0),

		.out_clk(out_clk),
		.shift_sync(shift_sync),
		.display_sync(display_sync),

		.force_sync(force_sync),
		.shift_cycle_adj(shift_cycle_adj),
		.more_adj_flag(more_adj_flag),

		.r_frame_sync(r_frame_sync),
		.scan_num(scan_num),
		.unit_num(unit_num),
		.bit_num(bit_num),
		.color_count(color_count),
		.obuf_sel(obuf_sel),
		.obuf_sync(obuf_sync),
		.obuf_raddr(obuf_raddr),
		.obuf_rdata(obuf_rdata),
		
		.cascade_light(cascade_light),
		.color2_pixel(pixel_mode[1]),
		.unit_l_max(unit_l_max),
		.data_inv_en(data_inv_en),
		.unit_type(unit_type),
		.scan_h_max(scan_h_max),
                .signal_ctrl(signal_ctrl),
                .shift_length_per_unit(shift_length_per_unit),
                .port_20_en(port_20_en),
                .port_24_en(port_24_en),
                //.mode_port_free(1'b0),
                .mode_port_free(mode_port_free),
                .SR_set(SR_set),
                .correct_type(correct_type),
                                
		.o_sclk(o_sclk),
		.o_load(o_load),
		.o_loeb(o_loeb),
		.o_h_sel(o_h_sel),
		.o_hoeb(o_hoeb),
		.o_data(o_data),
		
		.o_sync_flag(o_sync_flag),
		.testmode_ini_err(testmode_ini_err),
		.tout(o_tout)
		);

//强制同步
sync_595_ctrl_01 sync_ctrl(
		.resetb(resetb),
		.sclk(sclk),
		
		.set_d_ok(set_d_ok),
		.set_addr(set_addr),
		.set_data(set_data),
		
		.state_2(state_2),
		.vsin(vs_a),

		.out_clk(out_clk),
		.shift_sync(shift_sync),
		.display_sync(display_sync),
		
		.force_sync(force_sync),
		.shift_cycle_adj(shift_cycle_adj),
		.more_adj_flag(more_adj_flag),

		.tout(sync_tout)
		);
*/